H8SX1663 datasheet(234/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 182 of 1102

REJ09B0294-0100

(d) Address/data multiplexed I/O interface

The number of access cycles in data cycle of the address/data multiplexed I/O interface is the

same as that in the basic bus interface. The number of access cycles in address cycle can be

specified as two or three cycles by the ADDEX bit in MPXCR.

Number of access cycles in the address/data multiplexed I/O interface

= number of address output cycles (2, 3) + number of data output cycles (2, 3)

+ number of program wait cycles (0 to 7)

+ number of

CS extension cycles (0, 1, 2)

[+number of external wait cycles by the

WAIT pin]

(e)

DRAM Interface

In the DRAM interface, the numbers of precharge cycles, row address output cycles, and column

address output cycles can be specified.

The number of precharge cycles can be specified as one to four cycles by bits TPC1 and TPC0 in

DRACCR. The number of row address output cycles can be specified as one to four cycles by bits

RCD1 and RCD0 in DRACCR. The number of column address output cycles can be specified as

two or three cycles by the CAST bit in DRAMCR. For the column address output cycle, program

wait (0 to 7 cycles) specified by WTCRB or external wait by

WAIT can be inserted.

Number of access cycles in the DRAM interface

= number of precharge cycles (1 to 4) + number of row address output cycles (1 to 4)

+ number of column address output cycles (2 or 3)

+ number of program wait cycles (0 to 7)

[+number of external wait cycles by the WAIT pin]

(f)

SDRAM Interface

In the SDRAM interface, the numbers of precharge cycles, row address output cycles, and column

address output cycles, as well as clock suspend and write-precharge delay, can be specified by

DRACCR and WTCRB.

The number of precharge cycles can be specified as one to four cycles by bits TPC1 and TPC0 in

DRACCR. The number of row address output cycles can be specified as one to four cycles by bits

RCD1 and RCD0 in DRACCR. The number of column address output cycles during read access

can be specified as two to four cycles by bits W21 and W20 in WTCRB.

The cycles for clock suspend and write-precharge delay can be inserted by bits CKSPE and

TRWL in SDCR.

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