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H8SX1663 数据表(PDF) 236 Page - Renesas Technology Corp

部件名 H8SX1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX1663 数据表(HTML) 236 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 184 of 1102
REJ09B0294-0100
(5) Strobe Assert/Negate Timings
The assert and negate timings of the strobe signals can be modified as well as number of access
cycles.
• Read strobe (RD) in the basic bus interface
• Chip select assertion period extension cycles in the basic bus interface
• Data transfer acknowledge (DACK3 to DACK0) output for DMAC single address transfers
6.5.5
Area and External Bus Interface
(1) Area 0
Area 0 includes on-chip ROM. All of area 0 is used as external address space in on-chip ROM
disabled extended mode, and the space excluding on-chip ROM is external address space in on-
chip ROM enabled extended mode.
When area 0 external address space is accessed, the
CS0 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or burst ROM interface can be
selected for area 0 by bit BSRM0 in BROMCR and bit BCSEL0 in SRAMCR. Table 6.7 shows
the external interface of area 0.
Table 6.7
Area 0 External Interface
Register Setting
Interface
BSRM0 of BROMCR
BCSEL0 of SRAMCR
Basic bus interface
0
0
Byte control SRAM interface
0
1
Burst ROM interface
1
0
Setting prohibited
1
1



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