H8SX1663 datasheet(263/1158 Pages) RENESAS

部件名	H8SX1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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263 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 211 of 1102

REJ09B0294-0100

6.7.6

Read Strobe (

RD)

When the byte control SRAM space is specified, the RDNCR setting for the corresponding space

is invalid.

The read strobe negation timing is the same timing as when RDNn = 1 in the basic bus interface.

Note that the

RD timing with respect to the DACK rising edge becomes different.

6.7.7

Extension of Chip Select (

CS) Assertion Period

In the byte control SRAM interface, the extension cycles can be inserted before and after the bus

cycle in the same way as the basic bus interface. For details, refer to section 6.6.6, Extension of

Chip Select (

CS) Assertion Period.

6.7.8

DACK Signal Output Timing

For DMAC single address transfers, the

DACK signal assert timing can be modified by using the

DKC bit in BCR1.

Figure 6.28 shows the

DACK signal output timing. Setting the DKC bit to 1 asserts the DACK

signal a half cycle earlier.

H8SX1663 数据表(PDF) 263 Page - Renesas Technology Corp