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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX1663 数据表(PDF) 267 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 267 Page - Renesas Technology Corp |
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267 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 215 of 1102 REJ09B0294-0100 6.8.4 Basic Timing The number of access cycles in the initial cycle (full access) on the burst ROM interface is determined by the basic bus interface settings in ABWCR, ASTCR, WTCRA, WTCRB, and bits CSXHn in CSACR (n = 0 to 7). When area 0 or area 1 designated as burst ROM space is read by the CPU, the settings in RDNCR and bits CSXTn in CSACR (n = 0 to 7) are ignored. From one to eight cycles can be selected for the burst cycle, according to the settings of bits BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait cycles cannot be inserted. In addition, 4-word, 8-word, 16-word, or 32-word consecutive burst access can be performed according to the settings of BSTS01, BSTS00, BSTS11, and BSTS10 bits in BROMCR. The basic access timing for burst ROM space is shown in figures 6.29 and 6.30. T 1 T 2 T 1 T 2 T 1 T 2 T 3 B φ Upper address bus Note: n = 1, 0 Lower address bus Data bus Full access Burst access CSn AS RD BS RD/ WR Figure 6.29 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles) |
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