H8SX1663 datasheet(270/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 218 of 1102

REJ09B0294-0100

6.9

Address/Data Multiplexed I/O Interface

If areas 3 to 7 of external address space are specified as address/data multiplexed I/O space in this

LSI, the address/data multiplexed I/O interface can be performed. In the address/data multiplexed

I/O interface, peripheral LSIs that require the multiplexed address/data can be connected directly

to this LSI.

6.9.1

Address/Data Multiplexed I/O Space Setting

Address/data multiplexed I/O interface can be specified for areas 3 to 7. Each area can be

specified as the address/data multiplexed I/O space by setting bits MPXEn (n = 3 to 7) in

MPXCR.

6.9.2

Address/Data Multiplex

In the address/data multiplexed I/O space, data bus is multiplexed with address bus. Table 6.18

shows the relationship between the bus width and address output.

Table 6.18

Address/Data Multiplex

Bus Width

Cycle

Data Pins

Address

Data

Address

Data

8 bits

16 bits

PI7

A15

D15

PI6

A14

D14

PI5

A13

D13

PI4

A12

D12

PI3

A11

D11

PI2

A10

D10

PI1

PI0

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

6.9.3

Data Bus

The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access

space or 16-bit access space by the ABWHn and ABWLn bits (n = 3 to 7) in ABWCR.

For the 8-bit access space, D7 to D0 are valid for both address and data. For 16-bit access space,

D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is

accessed, the corresponding address will be output to the address bus.

For details on access size and data alignment, see section 6.5.6, Endian and Data Alignment.

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