ZUSBOPTSC01ZACG datasheet(62/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

GPIO Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

Port A–D Address Registers

The Port A–D Address registers select the GPIO port functionality accessible through the

Port A–D Control registers. The Port A–D Address and Control registers combine to pro-

vide access to all GPIO port controls; see Tables 18 and 19.

Table 18. Port A–D GPIO Address Registers (PxADDR)

Bit

Field

PADDR[7:0]

RESET

00H

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

FD0H, FD4H, FD8H, FDCH

Bit

Description

[7:0]



PADDRx

Port Address

The Port Address selects one of the subregisters accessible through the Port Control Register.

Note: x indicates the specific GPIO port pin number (7–0).

Table 19. Port A–D GPIO Address Registers by Bit Description

PADDR[7:0]

Port Control Subregister accessible using the Port A–D Control Registers

00H

No function. Provides some protection against accidental port reconfiguration.

01H

Data Direction.

02H

Alternate Function.

03H

Output Control (Open-Drain).

04H

High Drive Enable.

05H

Stop Mode Recovery Source Enable.

06H

Pull-up Enable.

07H

Alternate Function Set 1.

08H

Alternate Function Set 2.

09H–FFH

No function.

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