ZUSBOPTSC01ZACG datasheet(54/282 Pages) ZILOG

54 / 282 page

PS022827-1212

P R E L I M I N A R Y

Architecture

Z8 Encore! XP® F082A Series

Product Specification

Architecture

Figure 7 displays a simplified block diagram of a GPIO port pin. In this figure, the ability

to accommodate alternate functions and variable port current drive strength is not dis-

played.

GPIO Alternate Functions

Many of the GPIO port pins can be used for general-purpose I/O and access to on-chip

peripheral functions such as the timers and serial communication devices. The Port A–D

Alternate Function subregisters configure these pins for either General-Purpose I/O or

alternate function operation. When a pin is configured for alternate function, control of the

port pin direction (input/output) is passed from the Port A–D Data Direction registers to

the alternate function assigned to this pin. Table 15 on page 40 lists the alternate functions

possible with each port pin. For those pins with more one alternate function, the alternate

function is defined through Alternate Function Sets subregisters AFS1 and AFS2.

The crystal oscillator functionality is not controlled by the GPIO block. When the crystal

oscillator is enabled in the oscillator control block, the GPIO functionality of PA0 and PA1

is overridden. In that case, those pins function as input and output for the crystal oscillator.

Figure 7. GPIO Port Pin Block Diagram

GND

VDD

Port Output Control

Port Data Direction

Port Output

Data Register

Port Input

Data Register

Port

DATA

Bus

System

Clock

System

Clock

Schmitt-Trigger

ZUSBOPTSC01ZACG 数据表(PDF) 54 Page - Zilog, Inc.

ZUSBOPTSC01ZACG 数据表(HTML) 54 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载