ZUSBOPTSC01ZACG datasheet(72/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

GPIO Mode Interrupt Controller

Z8 Encore! XP® F082A Series

Product Specification

GPIO Mode Interrupt Controller

The interrupt controller on the Z8 Encore! XP F082A Series products prioritizes the inter-

rupt requests from the on-chip peripherals and the GPIO port pins. The features of inter-

rupt controller include:

•

20 possible interrupt sources with 18 unique interrupt vectors:

–

Twelve GPIO port pin interrupt sources (two interrupt vectors are shared)

–

Eight on-chip peripheral interrupt sources (two interrupt vectors are shared)



•

Flexible GPIO interrupts:

–

Eight selectable rising and falling edge GPIO interrupts

–

Four dual-edge interrupts



•

Three levels of individually programmable interrupt priority

•

Watchdog Timer and LVD can be configured to generate an interrupt

•

Supports vectored and polled interrupts



Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly

manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt

service routine is involved with the exchange of data, status information, or control infor-

mation between the CPU and the interrupting peripheral. When the service routine is com-

pleted, the CPU returns to the operation from which it was interrupted.

The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,

the interrupt controller has no effect on operation. For more information about interrupt

servicing by the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is

available for download on www.zilog.com.

Interrupt Vector Listing

Table 34 lists all of the interrupts available in order of priority. The interrupt vector is

stored with the most-significant byte (MSB) at the even Program Memory address and the

least-significant byte (LSB) at the following odd Program Memory address.

Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt is

unavailable on devices not containing an ADC.

Note:

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