ZUSBOPTSC01ZACG datasheet(69/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

GPIO Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

Port A–C Input Data Registers

Reading from the Port A–C Input Data registers, shown in Table 29, return the sampled

values from the corresponding port pins. The Port A–C Input Data registers are read-only.

The value returned for any unused ports is 0. Unused ports include those missing on the 8-

and 28-pin packages, as well as those missing on the ADC-enabled 28-pin packages.

Port A–D Output Data Register

The Port A–D Output Data Register, shown in Table 30, controls the output data to the pins.

Table 29. Port A–C Input Data Registers (PxIN)

Bit

Field

PIN7

PIN6

PIN5

PIN4

PIN3

PIN2

PIN1

PIN0

RESET

XXXXXXXX

R/W

RRRRRRR

Address

FD2H, FD6H, FDAH

X = Undefined.

Bit

Description

[7:0]



PxIN

Port Input Data

Sampled data from the corresponding port pin input.

0 = Input data is logical 0 (Low).

1 = Input data is logical 1 (High).

Note: x indicates the specific GPIO port pin number (7–0).

Table 30. Port A–D Output Data Register (PxOUT)

Bit

Field

POUT7

POUT6

POUT5

POUT4

POUT3

POUT2

POUT1

POUT0

RESET

00000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

FD3H, FD7H, FDBH, FDFH

Bit

Description

[7:0]



PxOUT

Port Output Data

These bits contain the data to be driven to the port pins. The values are only driven if the corre-

sponding pin is configured as an output and the pin is not configured for alternate function operation.

0 = Drive a logical 0 (Low).

1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting

the corresponding Port Output Control Register bit to 1.

Note: x indicates the specific GPIO port pin number (7–0).

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