ZUSBOPTSC01ZACG datasheet(40/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Reset Types

Z8 Encore! XP® F082A Series

Product Specification

During a System Reset or Stop Mode Recovery, the Internal Precision Oscillator requires

4 µs to start up. Then the Z8 Encore! XP F082A Series device is held in Reset for 66

cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash

option bits, this reset period is increased to 5000 IPO cycles. When a reset occurs because

of a low voltage condition or Power-On Reset (POR), this delay is measured from the time

that the supply voltage first exceeds the POR level. If the external pin reset remains

asserted at the end of the reset period, the device remains in reset until the pin is deas-

serted.

At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor dis-

abled, except PD0 (or PA2 on 8-pin devices) which is shared with the reset pin. On reset,

the PD0 is configured as a bidirectional open-drain reset. The pin is internally driven low

during port reset, after which the user code may reconfigure this pin as a general purpose

output.

During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal

oscillator and Watchdog Timer oscillator continue to run.

Upon Reset, control registers within the Register File that have a defined Reset value are

loaded with their reset values. Other control registers (including the Stack Pointer, Regis-

ter Pointer and Flags) and general-purpose RAM are undefined following Reset. The eZ8

CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads

that value into the Program Counter. Program execution begins at the Reset vector

address.

As the control registers are reinitialized by a system reset, the system clock after reset is

always the IPO. The software must reconfigure the oscillator control block, such that the

correct system clock source is enabled and selected.

Table 8. Reset and Stop Mode Recovery Characteristics and Latency

Reset Type

Reset Characteristics and Latency

Control Registers

eZ8

CPU

Reset Latency (Delay)

System Reset

Reset (as applicable)

Reset 66 Internal Precision Oscillator Cycles

System Reset with Crystal

Oscillator Enabled

Reset (as applicable)

Reset 5000 Internal Precision Oscillator Cycles

Stop Mode Recovery

Unaffected, except

WDT_CTL and

OSC_CTL registers

Reset 66 Internal Precision Oscillator Cycles

+ IPO startup time

Stop Mode Recovery with

Crystal Oscillator Enabled

Unaffected, except

WDT_CTL and

OSC_CTL registers

Reset 5000 Internal Precision Oscillator Cycles

ZUSBOPTSC01ZACG 数据表(PDF) 40 Page - Zilog, Inc.

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