ZUSBOPTSC01ZACG datasheet(63/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

GPIO Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

Port A–D Control Registers

The Port A–D Control registers set the GPIO port operation. The value in the correspond-

ing Port A–D Address Register determines which subregister is read from or written to by

a Port A–D Control Register transaction; see Table 20.

Port A–D Data Direction Subregisters

The Port A–D Data Direction subregister is accessed through the Port A–D Control Regis-

ter by writing 01H to the Port A–D Address Register; see Table 21.

Table 20. Port A–D Control Registers (PxCTL)

Bit

Field

PCTL

RESET

00H

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

FD1H, FD5H, FD9H, FDDH

Bit

Description

[7:0]



PCTLx

Port Control

The Port Control Register provides access to all subregisters that configure the GPIO port

operation.

Note: x indicates the specific GPIO port pin number (7–0).

Table 21. Port A–D Data Direction Subregisters (PxDD)

Bit

Field

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

RESET

11111111

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

If 01H in Port A–D Address Register, accessible through the Port A–D Control Register

Bit

Description

[7:0]



DDx

Data Direction

These bits control the direction of the associated port pin. Port Alternate Function operation

overrides the Data Direction Register setting.

0 = Output. Data in the Port A–D Output Data Register is driven onto the port pin.

1 = Input. The port pin is sampled and the value written into the Port A–D Input Data Register.

The output driver is tristated.

Note: x indicates the specific GPIO port pin number (7–0).

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