ZUSBOPTSC01ZACG datasheet(86/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Interrupt Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

Interrupt Control Register

The Interrupt Control (IRQCTL) Register, shown in Table 49, contains the master enable

bit for all interrupts.

Table 49. Interrupt Control Register (IRQCTL)

Bit

Field

IRQE

Reserved

RESET

00000000

R/W

RRRRRR

Address

FCFH

Bit

Description

[7]



IRQE

Interrupt Request Enable

This bit is set to 1 by executing an EI (Enable Interrupts) or IRET (Interrupt Return) instruction,

or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8

CPU acknowledgement of an interrupt request, Reset or by a direct register write of a 0 to this

bit.



0 = Interrupts are disabled.



1 = Interrupts are enabled.

[6:0]

Reserved

These bits are reserved and must be programmed to 0000000.

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