ZUSBOPTSC01ZACG datasheet(46/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Low Voltage Detection

Z8 Encore! XP® F082A Series

Product Specification

without initiating an interrupt (if enabled for that pin).

Stop Mode Recovery Using the External RESET Pin

When the Z8 Encore! XP F082A Series device is in STOP Mode and the external RESET

pin is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET

pin, the Low pulse must be greater than the minimum width specified, or it is ignored. See

the Electrical Characteristics chapter on page 226 for details.

Low Voltage Detection

In addition to the Voltage Brown-Out (VBO) Reset described above, it is also possible to

generate an interrupt when the supply voltage drops below a user-selected value. For

details about configuring the Low Voltage Detection (LVD) and the threshold levels avail-

able, see the Trim Option Bits at Address 0003H (TLVD) Register on page 166. The LVD

function is available on the 8-pin product versions only.

When the supply voltage drops below the LVD threshold, the LVD bit of the Reset Status

(RSTSTAT) Register is set to one. This bit remains one until the low-voltage condition

goes away. Reading or writing this bit does not clear it. The LVD circuit can also generate

an interrupt when so enabled, see the GPIO Mode Interrupt Controller chapter on page 55.

The LVD bit is not latched; therefore, enabling the interrupt is the only way to guarantee

detection of a transient low voltage event.

The LVD functionality depends on circuitry shared with the VBO block; therefore, dis-

abling the VBO also disables the LVD.

Reset Register Definitions

The following sections define the Reset registers.

Reset Status Register

The read-only Reset Status (RSTSTAT) Register, shown in Table 11, indicates the source

of the most recent Reset event, indicates a Stop Mode Recovery event and indicates a

Watchdog Timer time-out. Reading this register resets the upper four bits to 0. This regis-

ter shares its address with the write-only Watchdog Timer Control Register.

Table 12 lists the bit settings for Reset and Stop Mode Recovery events.

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