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ZUSBOPTSC01ZACG 数据表(PDF) 79 Page - Zilog, Inc. |
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ZUSBOPTSC01ZACG 数据表(HTML) 79 Page - Zilog, Inc. |
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79 / 282 page ![]() PS022827-1212 P R E L I M I N A R Y Interrupt Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 62 Interrupt Request 2 Register The Interrupt Request 2 (IRQ2) Register, shown in Table 37, stores interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 2 Register to determine if any interrupt requests are pending. IRQ0 Enable High and Low Bit Registers Table 38 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg- isters, shown in Tables 39 and 40, form a priority-encoded enabling for interrupts in the Interrupt Request 0 Register. Table 37. Interrupt Request 2 Register (IRQ2) Bit 7 6 5 4 3 2 1 0 Field Reserved PC3I PC2I PC1I PC0I RESET 00000000 R/W R/WR/W R/WR/WR/WR/WR/WR/W Address FC6H Bit Description [7:4] Reserved These bits are reserved and must be programmed to 0000. [3:0] PCxI Port C Pin x Interrupt Request 0 = No interrupt request is pending for GPIO Port C pin x. 1 = An interrupt request from GPIO Port C pin x is awaiting service. Note: x indicates the specific GPIO Port C pin number (0–3). Table 38. IRQ0 Enable and Priority Encoding IRQ0ENH[x]IRQ0ENL[x] Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Medium 1 1 Level 3 High Note: x indicates register bits 0–7. |
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