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ZUSBOPTSC01ZACG 数据表(PDF) 74 Page - Zilog, Inc. |
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ZUSBOPTSC01ZACG 数据表(HTML) 74 Page - Zilog, Inc. |
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74 / 282 page  PS022827-1212 P R E L I M I N A R Y Architecture Z8 Encore! XP® F082A Series Product Specification 57 Architecture Figure 8 displays the interrupt controller block diagram. Operation This section describes the operational aspects of the following functions. Master Interrupt Enable: see page 57 Interrupt Vectors and Priority: see page 58 Interrupt Assertion: see page 58 Software Interrupt Assertion: see page 59 Watchdog Timer Interrupt Assertion: see page 59 Master Interrupt Enable The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables and disables interrupts. Interrupts are globally enabled by any of the following actions: • Execution of an EI (Enable Interrupt) instruction • Execution of an IRET (Return from Interrupt) instruction Figure 8. Interrupt Controller Block Diagram Vector IRQ Request High Priority Medium Priority Low Priority Priority Mux Port Interrupts Internal Interrupts |
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