ZUSBOPTSC01ZACG datasheet(76/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Operation

Z8 Encore! XP® F082A Series

Product Specification

Example 1.

A poor coding style that can result in lost interrupt requests:

LDX r0, IRQ0



AND r0, MASK



LDX IRQ0, r0



To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt

Request 0 Register:

Example 2.

A good coding style that avoids lost interrupt requests:

ANDX IRQ0, MASK

Software Interrupt Assertion

Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt

Request Register triggers an interrupt (assuming that interrupt is enabled). When the inter-

rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request Register is

automatically cleared to 0.

Zilog recommends not using a coding style to generate software interrupts by setting bits

in the Interrupt Request registers. All incoming interrupts received between execution of

the first LDX command and the final LDX command are lost. See Example 3, which fol-

lows.

Example 3.

A poor coding style that can result in lost interrupt requests:

LDX r0, IRQ0



OR r0, MASK



LDX IRQ0, r0

To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt

Request registers:

Example 4.

A good coding style that avoids lost interrupt requests:

ORX IRQ0, MASK

Watchdog Timer Interrupt Assertion

The Watchdog Timer interrupt behavior is different from interrupts generated by other

sources. The Watchdog Timer continues to assert an interrupt as long as the time-out con-

dition continues. As it operates on a different (and usually slower) clock domain than the

rest of the device, the Watchdog Timer continues to assert this interrupt for many system

clocks until the counter rolls over.

Caution:

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