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ZUSBOPTSC01ZACG 数据表(PDF) 36 Page - Zilog, Inc. |
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ZUSBOPTSC01ZACG 数据表(HTML) 36 Page - Zilog, Inc. |
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36 / 282 page ![]() PS022827-1212 P R E L I M I N A R Y Register Map Z8 Encore! XP® F082A Series Product Specification 19 Timer 1 F08 Timer 1 High Byte T1H 00 90 F09 Timer 1 Low Byte T1L 01 90 F0A Timer 1 Reload High Byte T1RH FF 91 Timer 1 (cont’d) F0B Timer 1 Reload Low Byte T1RL FF 91 F0C Timer 1 PWM High Byte T1PWMH 00 92 F0D Timer 1 PWM Low Byte T1PWML 00 92 F0E Timer 1 Control 0 T1CTL0 00 85 F0F Timer 1 Control 1 T1CTL1 00 86 F10–F6F Reserved — XX UART F40 UART Transmit/Receive Data registers TXD, RXD XX 115 F41 UART Status 0 Register U0STAT0 00 114 F42 UART Control 0 Register U0CTL0 00 110 F43 UART Control 1 Register U0CTL1 00 110 F44 UART Status 1 Register U0STAT1 00 115 F45 UART Address Compare Register U0ADDR 00 116 F46 UART Baud Rate High Byte Register U0BRH FF 117 F47 UART Baud Rate Low Byte Register U0BRL FF 117 Analog-to-Digital Converter (ADC) F70 ADC Control 0 ADCCTL0 00 134 F71 ADC Control 1 ADCCTL1 80 136 F72 ADC Data High Byte ADCD_H XX 137 F73 ADC Data Low Byte ADCD_L XX 137 F74–F7F Reserved — XX Low Power Control F80 Power Control 0 PWRCTL0 80 34 F81 Reserved — XX LED Controller F82 LED Drive Enable LEDEN 00 53 F83 LED Drive Level High Byte LEDLVLH 00 53 F84 LED Drive Level Low Byte LEDLVLL 00 54 Table 7. Register File Address Map (Continued) Address (Hex) Register Description Mnemonic Reset (Hex) Page Notes: 1. XX = Undefined. 2. Refer to the eZ8 CPU Core User Manual (UM0128). |
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