ZUSBOPTSC01ZACG datasheet(13/282 Pages) ZILOG

13 / 282 page

PS022827-1212

P R E L I M I N A R Y

List of Tables

Z8 Encore! XP® F082A Series

Product Specification

xiii

List of Tables

Table 1.

Z8 Encore! XP F082A Series Family Part Selection Guide . . . . . . . . . . . . . 2

Table 2.

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3.

Pin Characteristics (20- and 28-pin Devices) . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4.

Pin Characteristics (8-Pin Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5.

Z8 Encore! XP F082A Series Program Memory Maps . . . . . . . . . . . . . . . . 16

Table 6.

Z8 Encore! XP F082A Series Flash Memory Information Area Map . . . . . 17

Table 7.

Table 8.

Reset and Stop Mode Recovery Characteristics and Latency . . . . . . . . . . . 23

Table 9.

Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 10.

Stop Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . . 28

Table 11.

Reset Status Register (RSTSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12.

Reset and Stop Mode Recovery Bit Descriptions . . . . . . . . . . . . . . . . . . . . 31

Table 13.

Power Control Register 0 (PWRCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14.

Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 36

Table 15.

Port Alternate Function Mapping (Non 8-Pin Parts) . . . . . . . . . . . . . . . . . . 40

Table 16.

Port Alternate Function Mapping (8-Pin Parts) . . . . . . . . . . . . . . . . . . . . . . 43

Table 17.

GPIO Port Registers and Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 18.

Port A–D GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . 45

Table 19.

Port A–D GPIO Address Registers by Bit Description . . . . . . . . . . . . . . . . 45

Table 20.

Port A–D Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 21.

Port A–D Data Direction Subregisters (PxDD) . . . . . . . . . . . . . . . . . . . . . . 46

Table 22.

Port A–D Alternate Function Subregisters (PxAF) . . . . . . . . . . . . . . . . . . . 47

Table 23.

Port A–D Output Control Subregisters (PxOC) . . . . . . . . . . . . . . . . . . . . . 48

Table 24.

Port A–D High Drive Enable Subregisters (PxHDE) . . . . . . . . . . . . . . . . . 48

Table 25.

Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE) . . 49

Table 26.

Port A–D Pull-Up Enable Subregisters (PxPUE) . . . . . . . . . . . . . . . . . . . . 50

Table 27.

Port A–D Alternate Function Set 2 Subregisters (PxAFS2) . . . . . . . . . . . . 51

Table 28.

Port A–D Alternate Function Set 1 Subregisters (PxAFS1) . . . . . . . . . . . . 51

ZUSBOPTSC01ZACG 数据表(PDF) 13 Page - Zilog, Inc.

ZUSBOPTSC01ZACG 数据表(HTML) 13 Page - Zilog, Inc.

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