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ZUSBOPTSC01ZACG 数据表(PDF) 83 Page - Zilog, Inc. |
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ZUSBOPTSC01ZACG 数据表(HTML) 83 Page - Zilog, Inc. |
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83 / 282 page ![]() PS022827-1212 P R E L I M I N A R Y Interrupt Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 66 Table 44. IRQ2 Enable and Priority Encoding IRQ2ENH[x]IRQ2ENL[x] Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Medium 1 1 Level 3 High Note: x indicates register bits 0–7. Table 45. IRQ2 Enable High Bit Register (IRQ2ENH) Bit 7 6 5 4 3 2 1 0 Field Reserved C3ENH C2ENH C1ENH C0ENH RESET 00000000 R/W R/WR/W R/WR/WR/WR/WR/WR/W Address FC7H Bit Description [7:4] Reserved These bits are reserved and must be programmed to 0000. [3] C3ENH Port C3 Interrupt Request Enable High Bit [2] C2ENH Port C2 Interrupt Request Enable High Bit [1] C1ENH Port C1 Interrupt Request Enable High Bit [0] C0ENH Port C0 Interrupt Request Enable High Bit |
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