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ZUSBOPTSC01ZACG 数据表(PDF) 66 Page - Zilog, Inc. |
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ZUSBOPTSC01ZACG 数据表(HTML) 66 Page - Zilog, Inc. |
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66 / 282 page ![]() PS022827-1212 P R E L I M I N A R Y GPIO Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 49 Port A–D Stop Mode Recovery Source Enable Subregisters The Port A–D Stop Mode Recovery Source Enable Subregister, shown in Table 25, is accessed through the Port A–D Control Register by writing 05H to the Port A–D Address Register. Setting the bits in the Port A–D Stop Mode Recovery Source Enable subregisters to 1 configures the specified port pins as a Stop Mode Recovery source. During STOP Mode, any logic transition on a port pin enabled as a Stop Mode Recovery source initiates Stop Mode Recovery. Table 25. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE) Bit 7 6 5 4 3 2 1 0 Field PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0 RESET 00000000 R/W R/WR/W R/WR/WR/WR/WR/WR/W Address If 05H in Port A–D Address Register, accessible through the Port A–D Control Register Bit Description [7:0] PSMREx Port Stop Mode Recovery Source Enabled 0 = The port pin is not configured as a Stop Mode Recovery source. Transitions on this pin dur- ing STOP Mode do not initiate Stop Mode Recovery. 1 = The port pin is configured as a Stop Mode Recovery source. Any logic transition on this pin during STOP Mode initiates Stop Mode Recovery. Note: x indicates the specific GPIO port pin number (7–0). |
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