ZUSBOPTSC01ZACG datasheet(47/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Reset Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

Table 11. Reset Status Register (RSTSTAT)

Bit

Field

POR

STOP

WDT

EXT

Reserved

LVD

RESET

See descriptions below

00000

R/W

RRRRRRR

Address

FF0H

Bit

Description

[7]



POR

Power-On Reset Indicator

If this bit is set to 1, a Power-On Reset event occurs. This bit is reset to 0 if a WDT time-out or

Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read.

[6]



STOP

Stop Mode Recovery Indicator

If this bit is set to 1, a Stop Mode Recovery occurs. If the STOP and WDT bits are both set to 1,

the Stop Mode Recovery occurs because of a WDT time-out. If the STOP bit is 1 and the WDT

bit is 0, the Stop Mode Recovery was not caused by a WDT time-out. This bit is reset by a

Power-On Reset or a WDT time-out that occurred while not in STOP Mode. Reading this regis-

ter also resets this bit.

[5]



WDT

Watchdog Timer Time-Out Indicator

If this bit is set to 1, a WDT time-out occurs. A POR resets this pin. A Stop Mode Recovery

from a change in an input pin also resets this bit. Reading this register resets this bit. This read

must occur before clearing the WDT interrupt.

[4]



EXT

External Reset Indicator

If this bit is set to 1, a Reset initiated by the external RESET pin occurs. A Power-On Reset or

a Stop Mode Recovery from a change in an input pin resets this bit. Reading this register

resets this bit.

[3:1]

Reserved

These bits are reserved and must be programmed to 000.

[0]



LVD

Low Voltage Detection Indicator

If this bit is set to 1 the current state of the supply voltage is below the low voltage detection

threshold. This value is not latched but is a real-time indicator of the supply voltage level.

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