ZUSBOPTSC01ZACG datasheet(97/282 Pages) ZILOG

97 / 282 page

PS022827-1212

P R E L I M I N A R Y

Operation

Z8 Encore! XP® F082A Series

Product Specification

5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing

to the relevant interrupt registers. By default, the timer interrupt is generated for both

input capture and reload events. If appropriate, configure the timer interrupt to be gen-

erated only at the input capture event or the reload event by setting TICONFIG field

of the TxCTL0 Register.

6. Configure the associated GPIO port pin for the Timer Input alternate function.

7. Write to the Timer Control Register to enable the timer and initiate counting.

In CAPTURE Mode, the elapsed time from timer start to Capture event can be calculated

using the following equation:

CAPTURE RESTART Mode

In CAPTURE RESTART Mode, the current timer count value is recorded when the

acceptable external Timer Input transition occurs. The Capture count value is written to

the Timer PWM High and Low Byte registers. The timer input is the system clock. The

TPOL

bit in the Timer Control Register determines if the Capture occurs on a rising edge

or a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is

generated and the count value in the Timer High and Low Byte registers is reset to 0001H

and counting resumes. The INPCAP bit in TxCTL0 Register is set to indicate the timer

interrupt is because of an input capture event.

If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the

Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer

generates an interrupt, the count value in the Timer High and Low Byte registers is reset to

0001H

and counting resumes. The INPCAP bit in TxCTL0 Register is cleared to indicate

the timer interrupt is not caused by an input capture event.

Observe the following steps for configuring a timer for CAPTURE RESTART Mode and

initiating the count:

1. Write to the Timer Control Register to:

–

Disable the timer

–

Configure the timer for CAPTURE RESTART Mode by writing the TMODE bits

in the TxCTL1 Register and the TMODEHI bit in TxCTL0 Register

–

Set the prescale value

–

Set the Capture edge (rising or falling) for the Timer Input



2. Write to the Timer High and Low Byte registers to set the starting count value (typi-

cally 0001H).

Capture Elapsed Time (s)

Capture Value

Start Value

–

 Prescale



System Clock Frequency (Hz)

---------------------------------------------------------------------------------------------------

ZUSBOPTSC01ZACG 数据表(PDF) 97 Page - Zilog, Inc.

ZUSBOPTSC01ZACG 数据表(HTML) 97 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载