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ZUSBOPTSC01ZACG 数据表(PDF) 99 Page - Zilog, Inc.

部件名 ZUSBOPTSC01ZACG
功能描述  High-Performance 8-Bit Microcontrollers
PDF  282 Pages
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制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

ZUSBOPTSC01ZACG 数据表(HTML) 99 Page - Zilog, Inc.

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PS022827-1212
P R E L I M I N A R Y
Operation
Z8 Encore! XP® F082A Series
Product Specification
82
–
Set the initial logic level (High or Low) for the Timer Output alternate function, if
appropriate
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control Register to enable the timer and initiate counting.
In COMPARE Mode, the system clock always provides the timer input. The Compare
time can be calculated by the following equation:
GATED Mode
In GATED Mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control Register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001H and counting resumes (assuming the Timer Input signal remains asserted).
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
Observe the following steps for configuring a timer for GATED Mode and initiating the
count:
1. Write to the Timer Control Register to:
–
Disable the timer
COMPARE Mode Time (s)
Compare Value
Start Value
–
 Prescale
System Clock Frequency (Hz)
-----------------------------------------------------------------------------------------------------
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