ZUSBOPTSC01ZACG datasheet(103/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Timer Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

Timer 0–1 Control Register 1

The Timer 0–1 Control (TxCTL1) registers, shown in Table 51, enable and disable the

timers, set the prescaler value and determine the timer operating mode.

[6:5]



TICONFIG

Timer Interrupt Configuration

This field configures timer interrupt definition.

0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events.



10 = Timer Interrupt only on defined Input Capture/Deassertion Events.



11 = Timer Interrupt only on defined Reload/Compare Events.

[4]

Reserved

This bit is reserved and must be programmed to 0.

[3:1]



PWMD

PWM Delay Value

This field is a programmable delay to control the number of system clock cycles delay

before the Timer Output and the Timer Output Complement are forced to their active state.

000 = No delay.



001 = 2 cycles delay.



010 = 4 cycles delay.



011 = 8 cycles delay.



100 = 16 cycles delay.



101 = 32 cycles delay.



110 = 64 cycles delay.



111 = 128 cycles delay.

[0]



INPCAP

Input Capture Event

This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture Event.

0 = Previous timer interrupt is not a result of Timer Input Capture Event.



1 = Previous timer interrupt is a result of Timer Input Capture Event.

Table 51. Timer 0–1 Control Register 1 (TxCTL1)

Bit

Field

TEN

TPOL

PRES

TMODE

RESET

00000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

F07H, F0FH

Bit

Description

[7]



TEN

Timer Enable

0 = Timer is disabled.



1 = Timer enabled to count.

Bit

Description (Continued)

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