ZUSBOPTSC01ZACG datasheet(104/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Timer Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

[6]

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TPOL

Timer Input/Output Polarity

Operation of this bit is a function of the current operating mode of the timer.

ONE-SHOT Mode

When the timer is disabled, the Timer Output signal is set to the value of this bit. When the

timer is enabled, the Timer Output signal is complemented upon timer Reload.

CONTINUOUS Mode

When the timer is disabled, the Timer Output signal is set to the value of this bit. When the

timer is enabled, the Timer Output signal is complemented upon timer Reload.

COUNTER Mode

If the timer is enabled the Timer Output signal is complemented after timer reload.

0 = Count occurs on the rising edge of the Timer Input signal.

1 = Count occurs on the falling edge of the Timer Input signal.

PWM SINGLE OUTPUT Mode

0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output

is forced High (1) upon PWM count match and forced Low (0) upon reload.

1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Out-

put is forced Low (0) upon PWM count match and forced High (1) upon reload.

CAPTURE Mode

0 = Count is captured on the rising edge of the Timer Input signal.

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1 = Count is captured on the falling edge of the Timer Input signal.

COMPARE Mode

When the timer is disabled, the Timer Output signal is set to the value of this bit. When the

timer is enabled, the Timer Output signal is complemented upon timer Reload.

Bit

Description (Continued)

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