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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ZUSBOPTSC01ZACG 数据表(PDF) 80 Page - Zilog, Inc. |
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ZUSBOPTSC01ZACG 数据表(HTML) 80 Page - Zilog, Inc. |
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80 / 282 page  PS022827-1212 P R E L I M I N A R Y Interrupt Control Register Definitions Z8 Encore! XP® F082A Series Product Specification 63 Table 39. IRQ0 Enable High Bit Register (IRQ0ENH) Bit 7 6 5 4 3 2 1 0 Field Reserved T1ENH T0ENH U0RENH U0TENH Reserved Reserved ADCENH RESET 00000000 R/W R/WR/W R/WR/WR/WR/WR/WR/W Address FC1H Bit Description [7] Reserved This bit is reserved and must be programmed to 0. [6] T1ENH Timer 1 Interrupt Request Enable High Bit [5] T0ENH Timer 0 Interrupt Request Enable High Bit [4] U0RENH UART 0 Receive Interrupt Request Enable High Bit [3] U0TENH UART 0 Transmit Interrupt Request Enable High Bit [2:1] Reserved These bits are reserved and must be programmed to 00. [0] ADCENH ADC Interrupt Request Enable High Bit Table 40. IRQ0 Enable Low Bit Register (IRQ0ENL) Bit 7 6 5 4 3 2 1 0 Field Reserved T1ENL T0ENL U0RENL U0TENL Reserved Reserved ADCENL RESET 00000000 R/W R R/W R/W R/W R/W R R R/W Address FC2H Bit Description [7] Reserved This bit is reserved and must be programmed to 0. [6] T1ENL Timer 1 Interrupt Request Enable Low Bit [5] T0ENL Timer 0 Interrupt Request Enable Low Bit |
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