ZUSBOPTSC01ZACG datasheet(82/282 Pages) ZILOG

82 / 282 page

PS022827-1212

P R E L I M I N A R Y

Interrupt Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

See the Shared Interrupt Select Register (IRQSS) Register on page 68 for selection of

either the LVD or the comparator as the interrupt source.

IRQ2 Enable High and Low Bit Registers

Table 44 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-

isters, shown in Tables 44 and 45, form a priority-encoded enabling for interrupts in the

Interrupt Request 2 Register.

Table 42. IRQ1 Enable High Bit Register (IRQ1ENH)

Bit

Field

PA7VENH PA6CENH

PA5ENH

PA4ENH

PA3ENH

PA2ENH

PA1ENH

PA0ENH

RESET

00000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

FC4H

Bit

Description

[7]



PA7VENH

Port A Bit[7] or LVD Interrupt Request Enable High Bit

[6]



PA6CENH

Port A Bit[7] or Comparator Interrupt Request Enable High Bit

[5:0]



PAxENH

Port A Bit[x] Interrupt Request Enable High Bit

Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL)

Bit

Field

PA7VENL PA6CENL

PA5ENL

PA4ENL

PA3ENL

PA2ENL

PA1ENL

PA0ENL

RESET

00000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

FC5H

Bit

Description

[7]



PA7VENL

Port A Bit[7] or LVD Interrupt Request Enable Low Bit

[6]



PA6CENL

Port A Bit[6] or Comparator Interrupt Request Enable Low Bit

[5:0]



PAxENL

Port A Bit[x] Interrupt Request Enable Low Bit

ZUSBOPTSC01ZACG 数据表(PDF) 82 Page - Zilog, Inc.

ZUSBOPTSC01ZACG 数据表(HTML) 82 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载