ZUSBOPTSC01ZACG datasheet(44/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Stop Mode Recovery

Z8 Encore! XP® F082A Series

Product Specification

and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a

pulse four cycles in duration always triggers a reset.

While the RESET input pin is asserted Low, the Z8 Encore! XP F082A Series devices

remain in the Reset state. If the RESET pin is held Low beyond the System Reset time-

out, the device exits the Reset state on the system clock rising edge following RESET pin

deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta-

tus bit in the Reset Status (RSTSTAT) Register is set to 1.

External Reset Indicator

During System Reset or when enabled by the GPIO logic (see Table 20 on page 46), the

RESET pin functions as an open-drain (active Low) reset mode indicator in addition to the

input functionality. This reset output feature allows a Z8 Encore! XP F082A Series device

to reset other components to which it is connected, even if that reset is caused by internal

sources such as POR, VBO or WDT events.

After an internal reset event occurs, the internal circuitry begins driving the RESET pin

Low. The RESET pin is held Low by the internal circuitry until the appropriate delay

listed in Table 8 has elapsed.

On-Chip Debugger Initiated Reset

A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in

the OCD Control Register. The On-Chip Debugger block is not reset but the rest of the

chip goes through a normal system reset. The RST bit automatically clears during the sys-

tem reset. Following the system reset the POR bit in the Reset Status (RSTSTAT) Register

is set.

Stop Mode Recovery

STOP Mode is entered by execution of a STOP instruction by the eZ8 CPU. See the Low-

Power Modes chapter on page 32 for detailed STOP Mode information. During Stop

Mode Recovery (SMR), the CPU is held in reset for 66 IPO cycles if the crystal oscillator

is disabled or 5000 cycles if it is enabled. The SMR delay (see Table 135 on page 233)

TSMR, also includes the time required to start up the IPO.

Stop Mode Recovery does not affect on-chip registers other than the Watchdog Timer

Control Register (WDTCTL) and the Oscillator Control Register (OSCCTL). After any

Stop Mode Recovery, the IPO is enabled and selected as the system clock. If another sys-

tem clock source is required, the Stop Mode Recovery code must reconfigure the oscillator

control block such that the correct system clock source is enabled and selected.

The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H

and loads that value into the Program Counter. Program execution begins at the Reset vec-

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