ZUSBOPTSC01ZACG datasheet(75/282 Pages) ZILOG

75 / 282 page

PS022827-1212

P R E L I M I N A R Y

Operation

Z8 Encore! XP® F082A Series

Product Specification

•

Writing a 1 to the IRQE bit in the Interrupt Control Register



Interrupts are globally disabled by any of the following actions:

•

Execution of a Disable Interrupt (DI) instruction

•

eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller

•

Writing a 0 to the IRQE bit in the Interrupt Control Register

•

Reset

•

Execution of a Trap instruction

•

Illegal Instruction Trap

•

Primary Oscillator Fail Trap

•

Watchdog Oscillator Fail Trap

Interrupt Vectors and Priority

The interrupt controller supports three levels of interrupt priority. Level 3 is the highest

priority, Level 2 is the second highest priority and Level 1 is the lowest priority. If all of

the interrupts are enabled with identical interrupt priority (all as Level 2 interrupts, for

example), the interrupt priority is assigned from highest to lowest as specified in Table 34

on page 56. Level 3 interrupts are always assigned higher priority than Level 2 interrupts

which, in turn, always are assigned higher priority than Level 1 interrupts. Within each

interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in

Table 34, above. Reset, Watchdog Timer interrupt (if enabled), Primary Oscillator Fail

Trap, Watchdog Oscillator Fail Trap and Illegal Instruction Trap always have highest

(level 3) priority.

Interrupt Assertion

Interrupt sources assert their interrupt requests for only a single system clock period (sin-

gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-

ing bit in the Interrupt Request Register is cleared until the next interrupt occurs. Writing a

0 to the corresponding bit in the Interrupt Request Register likewise clears the interrupt

request.

Zilog recommends not using a coding style that clears bits in the Interrupt Request reg-

isters. All incoming interrupts received between execution of the first LDX command and

the final LDX command are lost. See Example 1, which follows.

Caution:

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