ZUSBOPTSC01ZACG datasheet(61/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

GPIO Interrupts

Z8 Encore! XP® F082A Series

Product Specification

GPIO Interrupts

Many of the GPIO port pins can be used as interrupt sources. Some port pins can be con-

figured to generate an interrupt request on either the rising edge or falling edge of the pin

input signal. Other port pin interrupt sources generate an interrupt when any edge occurs

(both rising and falling). See the GPIO Mode Interrupt Controller chapter on page 55 for

more information about interrupts using the GPIO pins.

GPIO Control Register Definitions

Four registers for each port provide access to GPIO control, input data and output data.

Table 17 lists these port registers. Use the Port A–D Address and Control registers

together to provide access to subregisters for port configuration and control.

Table 17. GPIO Port Registers and Subregisters

Port Register Mnemonic

Port Register Name

PxADDR

Port A–D Address Register; selects subregisters.

PxCTL

Port A–D Control Register; provides access to subregisters.

PxIN

Port A–D Input Data Register.

PxOUT

Port A–D Output Data Register.

Port Subregister Mnemonic

Port Register Name

PxDD

Data Direction.

PxAF

Alternate Function.

PxOC

Output Control (Open-Drain).

PxHDE

High Drive Enable.

PxSMRE

Stop Mode Recovery Source Enable.

PxPUE

Pull-up Enable.

PxAFS1

Alternate Function Set 1.

PxAFS2

Alternate Function Set 2.

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