ZUSBOPTSC01ZACG datasheet(84/282 Pages) ZILOG

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PS022827-1212

P R E L I M I N A R Y

Interrupt Control Register Definitions

Z8 Encore! XP® F082A Series

Product Specification

Interrupt Edge Select Register

The Interrupt Edge Select (IRQES) Register, shown in Table 47, determines whether an

interrupt is generated for the rising edge or falling edge on the selected GPIO Port A input

pin.

Table 46. IRQ2 Enable Low Bit Register (IRQ2ENL)

Bit

Field

Reserved

C3ENL

C2ENL

C1ENL

C0ENL

RESET

00000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

FC8H

Bit

Description

[7:4]

Reserved

These bits are reserved and must be programmed to 0000.

[3]



C3ENL

Port C3 Interrupt Request Enable Low Bit

[2]



C2ENL

Port C2 Interrupt Request Enable Low Bit

[1]



C1ENL

Port C1 Interrupt Request Enable Low Bit

[0]



C0ENL

Port C0 Interrupt Request Enable Low Bit

Table 47. Interrupt Edge Select Register (IRQES)

Bit

Field

IES7

IES6

IES5

IES4

IES3

IES2

IES1

IES0

RESET

00000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

FCDH

Bit

Description

[7:0]

IESx

Interrupt Edge Select x

0 = An interrupt request is generated on the falling edge of the PAx input.



1 = An interrupt request is generated on the rising edge of the PAx input.

Note: x indicates the specific GPIO port pin number (0–7).

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