STR720 datasheet(53/401 Pages) STMICROELECTRONICS

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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7.3.1

Priority Level Arbitration

The SIPL (Source Interrupt Priority Level) field in the SIRs (Source Interrupt Register)

provides the priority level of each of the 32 interrupt sources.

Every clock cycle all the pending interrupts (stored in the IPR register) and their priorities are

evaluated, and a winner channel (if any) is elected.

An interrupt requesting channel, to be the winner, must:

■

be enabled (IER - Interrupt Enable Register)

■

have the highest priority level related to the current interrupt requests, and higher than the

current one (CIPR - Current Interrupt Priority Register)

■

have the highest position in the chain of the pending interrupts with the same SIPL value

The CIPR provides the priority of the interrupt (IRQ type) currently serviced. CIPR is set to 0

(lowest priority) upon reset and can be modified during program execution, updating the

currently serviced (if it isn’t, the write operation has no effect).

For safe operations it’s better to disable the IRQ, before attempting to modify the CIPR

The interrupt arbitration is stopped as soon as an interrupt is accepted by the processor (i.e.

the IVR - Interrupt Vector Register is read and the interrupt service routine starts), and the

CIPR and CICR registers are updated (see Figure 8: INTx represents a generic interrupt

request of priority x).

One clock later, after the priority stack update, the arbitration starts once again.

Before exiting the interrupt service, the CPU has to clear the related interrupt pending bit in

the EIC, to communicate the end of interrupt; this is possible by writing a ‘1’ to the proper IPR

bit.

STR720 数据表(PDF) 53 Page - STMicroelectronics