STR720 datasheet(41/401 Pages) STMICROELECTRONICS

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STR720 - ARCHITECTURE OVERVIEW

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The RTC generates a configurable periodic tick (see Table 13, “IRQ Interrupt Vector

Summary,” on page 32 and Table 15, “Wake-up line sources,” on page 35) and a

programmable alarm.

Readable/Writable registers contain the time elapsed since clock start, measured as 30.52

µs

ticks on a 48 bit counter.

The counter overflow is not handled being higher than 200 years.

5.9 AHB-APB bridges

In order to reduce the power consumption of the overall core, AHB and A-APB are clocked

with different frequencies: AHB with an high frequency to have high transfer performance,

A-APB with a scaled down frequency in order to reduce power consumption. The AHB-APB

asynchronous bridge provides a resynchronization mechanism in order to enable master of

the AHB bus to access the APB peripherals. For information on the APB bridges mapping,

please refer to Section 6.3: APB Bridges Mapping on page 48.

Since the ratio between AHB and A-APB could be also 1/16, more than 32 AHB-cycles could

be necessary to access a peripheral.

Moreover, the AHB-APB asynchronous bridge also controls the clock and reset signals of the

peripherals connected to A-APB subsystem. The Peripheral Clock Gating (PCG) registers

allow to clock off independently any of the peripherals connected to the bridge.

For peripherals that do have both an AHB and APB interface but that do not support two

independent clock domains, as External Memory Interface (EMI) and DMA Controller

(DMAC), a synchronous APB bridge is also implemented (S-APB). This bridge is also used to

connect those APB peripherals having specific bandwidth requirements, in order to avoid the

synchronization overhead present in the Asynchronous APB bridge.

5.10 Clock Gating Control (CGC)

The Clock Gating Control block (CGC) is a bank of registers which can be used to activate

clock and reset signals for most AHB and S-APB peripheral. In this way only the peripherals

actually required by the application need to be clocked, while all the other ones can be kept

frozen or under reset so to reduce system power consumption. This block acts as a

complement to the similar feature implemented by the A-APB bridge on its peripherals.

For most of the peripherals connected to AHB or S-APB subsystems there are three bits

inside CGC block: reset on/off control, normal clock on/off control and debug clock on/off; an

identical situation exists for A-APB peripherals which use a similar structure found in A-APB

bridge. The list of controlled peripherals can be found in Table 83: Peripheral clock and reset

gating on page 366 where also their reset status can be found.

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