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STR720 - ARCHITECTURE OVERVIEW

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5 ARCHITECTURE OVERVIEW

This chapter is meant to give an overview of the peripherals available inside STR720, with the

dedicated STR720 customizations. STR720 peripherals can be divided in the following

groups:

■

AHB peripheral set. This set is composed of all peripherals requiring fast access and high

transfer throughput and it contains program RAM memory, boot-ROM memory, DMA

processor capable of transferring data between peripherals and memory, ATAPI interface

for IDE device connection, DRAMC controller allowing the usage of commercial SDRAM

banks as system memory, and EMI which enables a direct connection of external FLASH

memories for system boot or other external memory mapped devices. Two different

AHB-APB bridges enable access to the rest of STR720 peripheral set.

■

S-APB peripheral set. This set contains those system peripherals which require to run

synchronously with ARM720T core, due to performance requirements or ease of integration.

It is composed of an Enhanced Interrupt Controller (EIC) and a specific Wake-Up Interrupt

Unit (WIU) to extend ARM720T interrupt capabilities, a Reset-Clock Control Unit (RCCU) to

select between different system clock source options and implement all the power saving

modes, a Real Time Clock to keep timing during powerdown mode, a Real-Time clock

generator, and configurable I/O ports giving access to a large number of configurable pins.

■

A-APB peripheral set. This set contains most of system peripherals and it is designed to

run at a lower frequency independent from the ARM720T one, thus reducing the overall

power consumption. It is composed of a set of serial channels to implement different kind of

user interfaces (BSPI and UART), protocol specific serial interfaces as CAN and USB, a

4-channel A/D converter suitable for control-voltage monitoring, 2 independent Enhanced

Function Timers (EFT) which can be used as system scheduler, Watch DoG for system

reliability (WDG), and configurable I/O port.

In the following sections a brief overview of the STR720 system is given. For a more detailed

description of each peripheral, please refer to the related chapters.

5.1 Enhanced Interrupt Controller (EIC)

The ARM720T CPU provides two levels of interrupt:

■

FIQ (Fast Interrupt Request) for fast, low latency interrupt handling.

■

IRQ (Interrupt Request) for more general interrupts.

The Enhanced Interrupt Controller (EIC) implements the handling of multiple interrupt

channels, interrupt priority and automatic vectorization. It provides:

■

32 maskable interrupt channels, mapped on ARM720T interrupt request pin IRQ

■

32 interrupt vectors

■

3 maskable interrupt channels, mapped on ARM720T fast interrupt request pin FIQ.

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