STR720 datasheet(82/401 Pages) STMICROELECTRONICS

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STR720 - DMA CONTROLLER (DMAC)

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9.3 Functional Description

The DMA Controller is a single channel DMA Controller capable of servicing up to 2 data

streams. To reduce the gate count only one FIFO has been implemented which is shared

among the 2 data streams via the use of priority selection logic as outlined in Table 25 on

page 82.

DMA Request3 is multiplexed with 2 internal request lines which are selected when a memory

to memory transfer is required. The DMAC block diagram is shown in Figure 10

The DMA Controller can be used for a memory to memory transfer, a peripheral to memory

transfer or a memory to peripheral transfer.

A DMA data transfer consists of a sequence of DMA data burst transfers. There are two types

of burst transfers, the first one is from the source address to the DMA Controller and the

second one is from the DMA Controller to the destination address. Each data burst transfer is

characterized by the burst length (1, 4, 8, or 16 words) and by the word width (1 byte, 2 bytes

or 4 bytes). The DMA data transfer is complete when the programmed total number of bytes

has been transferred from the source address to the destination address (Terminal Count

The Control Logic is used to arbiter between the data streams. It selects the request from the

highest priority active data stream, passing the data from the chosen stream to and from the

FIFO as required. Each stream has a set of data stream registers which are used by the

Control Logic to determine source and destination addresses and the amount and format of

data to be transferred. They also provide various other control and status information.

The DMA data stream registers are all 16 bit wide and are accessed via the APB Bus. The

control logic can read all of these registers and can write some of them.

There is a single dedicated interrupt line from the DMA Controller to the EIC. It is driven by 4

internal interrupt flags (two per data stream) which are ored together. They work as follows:

Once a transfer for a specific stream is complete (this condition being detected by its Terminal

Count register going to zero) the interrupt flag for the data stream is set. The interrupt logic

then generates an interrupt to the EIC telling it that a request for one of the data streams has

been completed. At the same time this data stream is disabled (i.e. the DMA Controller clears

the enable bit of its control register). The status register must be read to determine which data

stream caused the interrupt to be raised. The DMA Controller can now safely reconfigure this

data stream (if required) for future transfers. A data stream can be re-enabled via a write to the

enable bit of the corresponding Control Register.

Table 25. DMA Request Priority

DMA Request

Priority

External2

External3 - Internal0/1

4 (Lowest)

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