STR720 datasheet(68/401 Pages) STMICROELECTRONICS

68 / 401 page

STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

68/401

Note

r5 is a generic register among those available, namely r0 up to r12. Since there is no

way to save SPSR directly into the ARM’s stack, the operation is executed in two

steps using r5 as transition help register.

■

The ISR Body routines.

■

A Footer routine to exit ISR. It must be:

1) LDMFD sp!,{lr}

Restore lr_sys for the system mode

2) MSR cpsr_c,#0xD2

Disable IRQ, move to IRQ mode

3) Clear pending bit in EIC (using the proper IPRx)

4) LDMFD sp!,{r5}

Restore r5

5) MSR spsr,r5

Restore Status register spsr

6) LDMFD sp!,{r5,lr} Restore status lr_irq and workspace

7) SUBS pc,lr,#4

Return from IRQ and interrupt reenabled

In the following two paragraphs some comments on the code lines introduced above and

some hints useful when realizing subroutines to be invoked by an ISR are reported.

7.6.1

Avoiding LR_sys and r5 registers content loss

A first example refers to a LR_sys content loss problem: it is assumed that an ISR without

instruction 5) in the header routine (and consequently without instruction 1) in the footer

routine) has just started; the following happens:

•

Instruction 4) is executed (so system mode is entered)

•

A subroutine is called with a BL instruction and LR_sys now contains the return address

A: the first subroutine instruction should store register LR_sys into the stack (the address

of this instruction is called B)

•

A higher priority interrupt starts before previous operation could be executed

•

New ISR stores address B into LR_irq and enters system mode

•

A new subroutine is called with a BL instruction: LR_sys is loaded with the new return

address C (this overwrites the previous value A!) which is now stored into the stack.

•

The highest priority ISR ends and address B is restored: now LR_sys value can be put

into the stack but its value has changed to address C (instead of A).

The work-around to avoid such a dangerous situation is to insert line 5) at the end of header

routine and consequently line 1) at the beginning of footer routine.

Similar reasons could lead register r5 to be corrupted. To fix this problem, lines 3) in header

and 4) in footer should be added.

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