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STR720 数据表(PDF) 83 Page - STMicroelectronics |
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STR720 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 401 page  STR720 - DMA CONTROLLER (DMAC) 83/401 The DMA FIFO block consists of a 16 32-bit words deep FIFO plus Data Pack and Data Unpack units. The purpose of the FIFO block is to accommodate bus latency and burst length, and to perform any packing or unpacking operations on the data that may be necessary to accommodate different data-out/data-in width ratios. DMA Request 3 is multiplexed with 2 internal request signals which can be used for a memory to memory data transfer. To allow their use, the ‘Mem2Mem’ bit in the control register must be Figure 10. DMA Controller block diagram Interrupt Logic AHB bus FIFO APB Slave Interface Control Logic AHB Master Interface DMA Requests 2 3 Interrupt Request to EIC Data Stream 2 Registers Data Stream 3 Registers APB bus 1 |
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