STR720 datasheet(95/401 Pages) STMICROELECTRONICS

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STR720 - DMA CONTROLLER (DMAC)

95/401

Interrupt Mask Register (DMAMask)

Address Offset: F0h

Reset value: 0000h

The DMA Mask Register is user to select the status flag that can generate an interrupt.

Bits 1:0 = Reserved. They must always be written to 0.

Bit 2 = SIM2: Stream 2 Interrupt Mask

This bit controls the generation of DMA interrupts triggered by stream 2 transfer end events.

1: Stream 2 transfer end interrupt is enabled

0: Stream 2 transfer end interrupt is masked

Bit 3 = SIM3: Stream 3 Interrupt Mask

This bit controls the generation of DMA interrupts triggered by stream 3 transfer end events.

1: Stream 3 transfer end interrupt is enabled

0: Stream 3 transfer end interrupt is masked

Bits 5:4 = Reserved. They must always be written to 0.

Bit 6 = SEM2: Stream 2 Error Mask

This bit controls the generation of DMA interrupts triggered by stream 2 transfer errors events.

1: Stream 2 transfer error interrupt is enabled

0: Stream 2 transfer error interrupt is masked

Bit 7 = SEM3: Stream 3 Error Mask

This bit controls the generation of DMA interrupts triggered by stream 3 transfer errors events.

1: Stream 3 transfer error interrupt is enabled

0: Stream 3 transfer error interrupt is masked

Bit 15:8 = Reserved. They must be always written to ‘0’

765432

reserved

SEM3

SEM2

res.

SIM3

SIM2

res.

rwrwrwrw

rwrw

STR720 数据表(PDF) 95 Page - STMicroelectronics

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