STR720 datasheet(38/401 Pages) STMICROELECTRONICS

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STR720 - ARCHITECTURE OVERVIEW

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5.7 Reset and Clock Control Unit (RCCU)

Reset and Clock Control Unit (RCCU) is responsible of the control and distribution of the reset

and the clocks signals of STR720.

5.7.1

Clock management

All possible operating modes (including low power ones) are managed by this peripheral by

selecting the system clock source and prescaling it so to adapt its frequency to actual system

requirements. A conceptual block diagram of RCCU clock management structure is reported

in Figure 5 on page 38

As the diagram reports, different clock frequencies can be used for the main system

composed by the AHB and the S-APB subsystems. As an example, when CLK clock is driven

by a 16 MHz signal, the following values are possible, for main system clock:

■

CLK: 16 MHz

■

CLK divided by 2

■

CLK divided by 32 or by 64

■

CLK multiplied by PLL (see RUN mode section)

■

CLK_AF source: 32 kHz oscillator output.

A programmable prescaler derives A-APB subsystem clock from main clock signal, while

independent and dedicated prescalers are implemented in order to generate the ATAPI clock.

All serial interfaces (CAN, BSPI, UART) have configurable internal prescalers in order to

generate the correct baud rates. Each peripheral inside STR720 system can be

Figure 5. RCCU Simplified Block Diagram

1/2

CLK

CLK2

CLK_AF

PLL

Clock Multiplier

Unit

/Divider

A-APB clock

AHB / S-APB clock

1/2, 1/4

1/32

ATAPI clock

OSCIN

(32 kHz)

DIV2

PLL_BYP

SLOW

IDLE

STOP

1/8, 1/16

1/2, 1/3

(ATAPI_CLK)

(AHB_CLK)

(APB_CLK)

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