STR720 datasheet(35/401 Pages) STMICROELECTRONICS

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STR720 - ARCHITECTURE OVERVIEW

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In STR720 implementation, the 10 internal wake-up lines are associated with the input of

serial communication modules and also with other relevant internal events, as defined in

Table 15. In this way, if properly programmed, the system can be woken up by the detection of

activity on any serial bus or when the external CLK restarts. For example, wake-up line 15

can be used to restore STR720 system when only the Real Time Clock is left running.

Note

Wake-up line 6 is associated to any change of PLL lock condition detected by RCCU

unit but, unlike all others, this wake-up line cannot be used to restore system from

STOP mode. It can be used as an interrupt extension line only.

Note

Wake-up line 7, associated to CLK clock, will be always set its corresponding

pending bit as long as the external clock is present.

5.3 DMA Controller (DMAC)

The DMA controller provides access to 2 data streams inside STR720 system. Since

peripherals are memory mapped, data transfers from/to peripherals are managed like

memory/memory data transfers.

Each data stream can be associated to one particular peripheral, which triggers a DMA

request starting the data transfer between the corresponding buffers defined in the stream

descriptor. Data stream 3 of DMA controller can alternatively be used as a memory/memory

data transfer triggered by a software DMA request, independently from any peripheral activity.

In case data stream 3 is also associated to a peripheral request, the two modes can be

selected by software.

The DMA controller supports circular buffer management avoiding the generation of interrupts

when the controller reach the end of the source buffer. When a stream is configured in circular

buffer mode and the end of buffer is reached, DMA controller reloads the start address and

continues the transfer until software notifies the end of operations.

The priority between different DMA triggering sources is defined by hardware, source 0 being

the highest priority request and source 3 being the lowest one. The mapping of DMA requests

Table 15. Wake-up line sources

Wake-up line #

Wake-up line source

RCCU: Change of PLL Lock condition (see note below).

CLK clock line

Port2.0: UART1 Receive Data Input (RxD1)

Port2.2: UART2 Receive Data Input (RxD2)

Port2.6: BSPI1. Slave Mode. Input serial clock (SCK1).

Port2.9: BSPI2. Slave Mode. Input serial clock (SCK2).

Port2.11: CAN module receive pin (CANRX).

Reserved.

USB wake-up event: generated while exiting from suspend mode.

RTC related event: Alarm Interrupt.

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