STR720 datasheet(48/401 Pages) STMICROELECTRONICS

48 / 401 page

STR720 - MEMORY ORGANIZATION

48/401

6.2 Memory map

6.3 APB Bridges Mapping

APB bridges allow the connection between the high performance AHB bus, where ARM720,

DMA, memory block and memory interfaces are located, to the peripherals residing on the

APB bus. Two separated APB subsystems have been implemented on STR720 device:

Asynchronous APB subsystem and Synchronous APB subsystem. They are briefly described

in the following sections, along with the related peripheral address mapping.

6.3.1

Asynchronous APB sub-system (A-APB)

In order to reduce the power consumption of the overall device, the Asynchronous APB

sub-system, in short A-APB, can be clocked at a frequency different from the one used for

ARM720T core. A specific asynchronous AHB-APB bridge provides a re-synchronization

mechanism in order to enable the master of AHB bus to access the APB peripherals although

residing on a different clock domain.

0x0000_0000

EMI

0x4000_0000

4 GBytes

Block 0

Block 1

Block 2

Block 3

Block 4

Block 5

ATAPI-IDE

Block 6

Block 7

0x6000_0000

0x8000_0000

0xA000_0000

0xC000_0000

0xE000_0000

4 GBytes

REMAP

Reset Memory Map

Remapped Memory Map

Non-implemented memory areas

0x2000_0000

SDRAM

0x2000_0FFF

0x6000_3FFF

0x0000_0000

EMI

0x4000_0000

Block 0

Block 1

Block 2

Block 3

Block 4

Block 5

ATAPI-IDE

Block 6

Block 7

0x6000_0000

0x8000_0000

0xA000_0000

0xC000_0000

0xE000_0000

0x2000_0000

SDRAM

0x2000_0FFF

0x0000_3FFF

0xF000_0000

A-APB

S-APB

0x6000_3FFF

0xF000_0000

A-APB

S-APB

Reserved

PROG RAM

ROM

STR720 数据表(PDF) 48 Page - STMicroelectronics

STR720 数据表(HTML) 48 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载