STR720 datasheet(49/401 Pages) STMICROELECTRONICS

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STR720 - MEMORY ORGANIZATION

49/401

The A-APB memory space decoding is provided by the A-APB bridge which assigns a 4

KBytes memory area to each peripheral. Table 20 reports the A-APB memory mapping.

Table 20. A-APB sub-system memory map

Peripheral Name

Start Address

End Address

Data

Size

Peripheral

Asynchronous AHB-APB Bridge (A3BRG) 0xE000_0000

0xE000_0FFF

Section 15.4.1

A-APB Global Control Register (A-GCR)

0xE000_1000

0xE000_1FFF

Section 24.5.1

General Purpose I/O 2 (GPIO2)

0xE000_2000

0xE000_2FFF

Section 23.4.1

Buffered Serial Port Interface 1 (BSPI1)

0xE000_3000

0xE000_3FFF

Section 17.4.1

Buffered Serial Port Interface 2 (BSPI2)

0xE000_4000

0xE000_4FFF

Section 17.4.1

Universal Async. Receiver/Transm. 1

(UART1)

0xE000_5000

0xE000_5FFF

Section 16.4.1

Universal Async. Receiver/Transm. 2

(UART2)

0xE000_6000

0xE000_6FFF

Section 16.4.1

Extended Function Timer 1 (EFT1)

0xE000_7000

0xE000_7FFF

Section 21.4.1

Extended Function Timer 2 (EFT2)

0xE000_8000

0xE000_8FFF

Section 21.4.1

Analog Digital Converter (ADC)

0xE000_9000

0xE000_9FFF

Section 22.4.1

Controller Area Network Interface (CAN)

0xE000_A000

0xE000_AFFF

Section 18.7.11

Universal Serial Bus Interface (USB)

0xE000_B000

0xE000_BFFF

Section 19.6.4

Watch-DoG (WDG)

0xE000_C000

0xE000_CFFF

Section 20.4.1

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