STR720 datasheet(36/401 Pages) STMICROELECTRONICS

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STR720 - ARCHITECTURE OVERVIEW

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implemented in STR720 system is detailed in Table 16. Where multiple sources are available

for a stream triggering event, the selection is performed by specific configuration bits located

in SGCR3 register. Note that ATAPI can be programmed so to transfer its data to/from

memory using the memory-to-memory transfer mode, so there is no need to generate a

specific request to the DMA controller.

The DMA controller treats bytes in memory as being in Little Endian format: the lowest

numbered byte in a word is considered the word least significant byte and the highest

numbered byte the most significant.

5.4 DRAM controller (DRAMC)

The STR720 device provides an SDRAM which supports four external banks containing

SDRAM memories, all banks being of the same DRAM type. Each bank can be enabled/

disabled through configuration registers and its size can vary between 64 KBytes and

32 MBytes. This allows the controller to address from 64 KBytes (1 bank of 64 KBytes) up to

128 MBytes (four banks of 32 MBytes). Due to pad number limitation, the maximum

addressable range of 128 MBytes (32 MBytes each bank) can be reached only when 32 bit

wide memories are used and column address is at least 9 bit long.

Accesses to the SDRAM memory are done using an AHB interface, while a dedicated APB

interface enables the CPU to configure various parameters of SDRAMC accesses to the

external memory as word and column size, data latency, setup time, idle time, bank enabling,

refresh period.

When ARM720 cache is enabled, all accesses to SDRAM memory are performed as bursts of

4 transfers on AHB bus and in order to achieve the highest performance level, SDRAM

interface must be aware of this peculiar access mode. Unfortunately a limitation in ARM720

core and SDRAM interface requires this specific configuration to be enforced explicitly by

software. This configuration selection is performed by using CACHE_CONFIG bit of SGCR1

whenever cache is enabled, so to have optimal performance from the system. See Section

10.5: Programming considerations on page 114 about SDRAM configuration, and Section

24.3: S-GCR Block description on page 352 for further details and limitations about the

usage of SDRAM “burst-access” mode.

Table 16. DMA request mapping

Stream

DMA triggering source

Reserved.

BSPI1 Receive data request

Memory-to-memory / BSPI1 Transmit data request / ADC

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