STR720 datasheet(46/401 Pages) STMICROELECTRONICS

46 / 401 page

STR720 - ARCHITECTURE OVERVIEW

46/401

Note1: to avoid power consumption the user has to drive the input pins to stable values.

JTAG input pins require special attention since they do not implement any internal resistor:

external devices should be connected to guarantee proper levels and to avoid possible

spurious consumption of the input logic and/or undesired malfunctioning of the JTAG module.

When the system is put into STOP mode, all the pins maintains the status previously

programmed while entering in STANDBY mode all pins are restored to their reset state.

5.20 Miscellanea Registers

The Miscellanea Registers module gathers all the registers that describe the current

configuration of STR720 system. They can be accessed through the APB interface and allow

a software configuration of some of the main features of the device. The complete list of

configurable features can be found in Chapter 24: MISCELLANEA REGISTERS (GCR - CGC

- AHB_ERR) on page 351. The most relevant features which can be configured are given

below.

■

Boot re-mapping (BRM) specifies where to find the boot program code. By default, it maps

the boot-ROM or EMI area to address 0x0000_0000 after reset.

■

DMA Stream selection bit (ST3_SEL) configure which peripherals will have access to DMA

request line 3.

■

Port7 Access Selection (P7AS) which enables to specify if Port7 is used for EMI or

ATAPI-IDE interface.

■

Address of last AHB transaction which resulted in a ERROR response (useful during

application debug).

TDI

Input

TDO

Output Tristate

Port1[0:3]

Analog Input

Port1[6:7]

High impedance

Port6[0:31]

Input

Port6[32:45]

Output

Port6[47]

Output

Port6[48]

Output

Port6[49:59]

Output

Port6[53:59]

Output

Port7[0:15]

Input

Port7[16:37]

Output

Port7[38:43]

Output

Port7[44:45]

Input

Table 19. Dedicated Pins Reset status

Pin (Note 1)

Status under Reset

Value under Reset

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