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6.3.2

Synchronous APB sub-system (S-APB)

Some peripherals require to be tightly coupled with ARM720 core for performance reasons

and some others have both AHB and APB ports, typically separating data from and control

information. In both cases it is required to have an APB sub-system which runs synchronously

with the AHB clock frequency. A plain AHB-APB bridge is used to connect these synchronous

APB peripherals to the system. The S-APB memory space decoding is provided by the S-APB

bridge which assigns a 1 KByte memory area to each peripheral. Table 21 reports the S-APB

memory mapping:

In order to provide an effective usage of EIC vectorized interrupt features, S-APB sub-system

is mapped on multiple address ranges: the first one starts from 0xF000_0000 and ends to

0xF000_3FFF then the first replica begins, using the addresses from 0xF000_4000 to

0xF000_7FFF and so on up to the last address range duplicate which extends from

0xFFFF_C000 to 0xFFFF_FFFF. Within this last S-APB address range image the EIC

registers appears starting from 0xFFFF_FC00, allowing to reach IVR register at absolute

address 0xFFFF_FC18, inside the range supported by the indirect jump instruction stored at

IRQ vector location (0x0000_0018).

Table 21. S-APB sub-system memory map

Peripheral name

Start Address

End Address

Data

Size

Peripheral

DRAM controller (DRAMC)

0xF000_0000

0xF000_03FF

Section 10.4.1

External Memory Interface (EMI)

0xF000_0400

0xF000_07FF

Section 11.4.1

Direct Memory Access Controller (DMAC)

0xF000_0800

0xF000_0BFF

Section 9.4.1

S-APB Global Control Register (S-GCR)

0xF000_0C00

0xF000_0FFF

Section 24.5.1

Reset and Clock Control Unit (RCCU)

0xF000_1000

0xF000_13FF

Section 13.4.1

General Purpose I/O 3 (GPIO3)

0xF000_1400

0xF000_17FF

Section 23.4.1

General Purpose I/O 4 (GPIO4)

0xF000_1800

0xF000_1BFF

Section 23.4.1

Reserved

0xF000_1C00

0xF000_1FFF

Reserved

0xF000_2000

0xF000_23FF

Wake-up/Interrupt Unit (WIU)

0xF000_2400

0xF000_27FF

Section 8.5

Real Time Clock (RTC)

0xF000_2800

0xF000_2BFF

Section 14.4.1

Clock gating control block (CGC)

0xF000_2C00

0xF000_2FFF

Section 24.5.1

AHB Error decoder (AERR)

0xF000_3000

0xF000_33FF

Section 24.5.1

Reserved

0xF000_3400

0xF000_37FF

Reserved

0xF000_3800

0xF000_3BFF

Enhanced Interrupt Controller (EIC)

0xF000_3C00

0xF000_3FFF

Section 7.4.1

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