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STR720 数据表(PDF) 29 Page - STMicroelectronics |
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STR720 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 401 page  STR720 - ARCHITECTURE OVERVIEW 29/401 Interrupt Vector 2 • Wake-up Controller interrupt request From 0 to 11 (the number of wake-up input alternate function pins) different interrupt requests are OR-ed together to generate a single interrupt request. Refer to Wake-up Controller specifications for further details on interrupt request generation. Interrupt Vector 3 • Extended Function Timer 1 interrupt request. Five different interrupt requests are OR-ed together to generate a single interrupt request: • Input Capture A • Output Compare A • Timer Overflow • Input Capture B • Output Compare B Interrupt Vector 4 • Extended Function Timer 2 interrupt request. Three different interrupt requests are OR-ed together to generate a single interrupt request: • Input Capture A • Timer Overflow • Input Capture B Interrupt Vector 5 • UART1 interrupt request Nine different interrupt requests are OR-ed together to generate a single interrupt request: • Receive buffer full • Transmit buffer empty • Transmit buffer half empty •Parity error •Frame error •Overrun error • Timeout not empty • Timeout idle • Receive buffer half full 1 |
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