STR720 datasheet(74/401 Pages) STMICROELECTRONICS

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STR720 - WAKE-UP INTERRUPT UNIT (WIU)

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8.4 Register description

Wake-up Control Register (WUCTRL)

Address Offset: 00h

Reset value: 0000h

Bit 15:3 = Reserved. These bits must be always written to 0.

Bit 2 = STOP: Stop bit.

To enter STOP Mode, write the sequence 1,0,1 to this bit with three write operations. When a

correct sequence is recognized, the STOP bit is set and RCCU puts the device in STOP Mode

(see Section 13: RESET AND CLOCK CONTROL UNIT (RCCU) on page 138). If the setting

sequence isn’t recognized within 64 clock periods, a TIMEOUT counter expires and reset the

sequence state machine, so the device doesn’t enter in STOP Mode and the STOP bit is reset

by hardware. The software sequence succeeds only if the following conditions are true:

•

the WKUP-INT bit is 1,

•

all unmasked pending bits are reset,

•

at least one mask bit is equal to 1 (at least one external wake-up line is not masked).

Otherwise the device cannot enter STOP mode, and the program continues the execution of

the code: the STOP bit remains cleared.

The bit is reset by hardware if, during STOP mode, a wake-up interrupt comes from any of the

unmasked wake-up lines. Otherwise the STOP bit is at 1 in the following cases (See

“Wake-up Mode Selection” on page 72. for details):

•

After the first write instruction of the sequence (a 1 is written to the STOP bit)

•

At the end of a successful sequence (i.e. after the third write instruction of the

sequence)

WARNING: If Interrupt requests are acknowledged during the sequence, the system will not

enter STOP mode (since the sequence is not completed): at the end of the interrupt service

routine, it is suggested to reset the sequence state machine. To reset the sequence it is

necessary to write twice a logic ‘0’ to the STOP bit of WUCTRL register (corresponding

anyway to a bad sequence); on the contrary the incomplete sequence is waiting for the

completion and only the TIMEOUT counter will reset the state machine. The user must

re-enter the sequence to set the STOP bit.

WARNING: Whenever a STOP request is issued to the system, a few clock cycles are needed

to enter STOP mode. Hence the execution of the instruction following the STOP bit setting

Reserved

STOP

INT_

WKUP

INT

-rw

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