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数据搜索系统，热门电子元器件搜索 |
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STR720 数据表(PDF) 62 Page - STMicroelectronics |
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STR720 数据表(HTML) 62 Page - STMicroelectronics |
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62 / 401 page  STR720 - ENHANCED INTERRUPT CONTROLLER (EIC) 62/401 Interrupt Enable Register 0 (IER0) Address Offset: 20h Reset value: 0000 0000h Bit 31 = IER[31]: Channel 31 Interrupt Enable bit Bit 30 = IER[30]: Channel 30 Interrupt Enable bit ... Bit 1 = IER[1]: Channel 1 Interrupt Enable bit Bit 0 = IER[0]: Channel 0 Interrupt Enable bit The IER0 is a 32 bit register: it provides an enable bit for each of the 32 EIC interrupt input channels. In order to enable the interrupt response to a specific interrupt input channel the corresponding bit in the IER0 register must be set to ‘1’. A ‘0’ value makes the EIC mask the related interrupt channel and the interrupt pending bit, in the IPR register, is never set. 1: Input channel enabled 0: Input channel disabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IER[31:16] rw 15 14 13 12 11 10 9 8 765432 1 0 IER[15:0] rw 1 |
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