STR720 datasheet(15/401 Pages) STMICROELECTRONICS

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STR720 - PIN DATA

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Note1: The signal applied to this pin is internally filtered by an on-chip RC filter whose width can range from 50 ns to

500 ns.

4.3 JTAG pins

In Table 4 the pins related to the JTAG interface are listed.

Note1: The signal applied to this pin is internally filtered by an on-chip RC filter whose width can range from 50 ns to

500 ns.

4.4 Port 1 pins

Port 1 is an analog port connected to the 4 analog input channels of the on-chip A/D converter

are available.

RTCRST(Note 1)

158

RTC RESET Input with Schmitt-Trigger characteristics.

A low level at this pin asynchronously resets the RTC registers.

Table 4. JTAG/Emu Pins

Symbol

I/O

Function

JTDO

ARM720 JTAG Test Data Out. JTDO is a test data serial output signal used for

test instructions and data.

JTCK

ARM720 JTAG Test Clock. JTCK is a test input used to synchronize the JTAG test

logic.

JTMS

ARM720 JTAG Test Mode Select. JTMS is an input signal used to sequence the

test controller’s state machine. JTMS is sampled on the rising edge of JTCK.

JTDI

ARM720 JTAG Test Data In. JTDI is test data serial input used for test instructions

and data. JTDI is sampled on the rising edge of JTCK.

JTRST (Note 1)

ARM720 JTAG Test Circuit Reset. JTRST is an active low Schmitt-trigger input

signal used to asynchronously initialize the test controller.

Table 5. Port 1 Pins

Symbol

I/O

Function

P1.0

A/D. Analog Input Channel 0 (ANA0).

P1.1

A/D. Analog Input Channel 1 (ANA1).

P1.2

A/D. Analog Input Channel 2 (ANA2).

P1.3

A/D. Analog Input Channel 3 (ANA3).

P1.4

Reserved.

P1.5

Reserved.

Table 3. Global Pins

Symbol

I/O

Function

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