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STR720 数据表(PDF) 67 Page - STMicroelectronics

部件名 STR720
功能描述  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STR720 数据表(HTML) 67 Page - STMicroelectronics

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)
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7.5 Programming considerations
Here are a few guideline steps on how to program the EIC’s registers in order to get the
controller up and running quickly. In the following, it is assumed to deal with standard
interrupts and that the user wants, for example, to detect an interrupt on channel #22, in which
the priority has been assigned to be 5.
First of all, it is necessary to assign the priority and the jump address data related to the
interrupt channel #22. Therefore:
set in field SIPL of SIR22 the binary “0101”, i.e. priority of 5 (it must be not 0 to have an IRQ
to be generated).
Two registers are involved to supply the channel interrupt vector data to the EIC controller
(IVR[31:16] and SIR22[31:16]:
write in SIR22[31:16], i.e. in the upper part of the SIR register related to channel #22, the
memory address offset (or the jump offset) where the Interrupt Service Routine, related to
interrupt channel #7, starts.
insert the base jump address (or the jump opcode) in the most significant half of the IVR
register, i.e. IVR[31:16].
Finally, response to the interrupt must be enabled both at the global level and at the single
interrupt channel level. To do so these steps shall be followed:
set the IRQ_EN bit of ICR to 1
set bit # 22 of IER0 to 1
As far as the FIQ interrupts are concerned, since those interrupts do not have any
vectorization nor priority, only the first two steps above are involved. Supposing the user wants
to enable FIQ channel #1:
set the FIQ_EN bit of ICR to 1.
set bit #1 of FIE in FIR register to 1.
7.6 Application note
Every Interrupt Service Routine (ISR) should be composed by the following blocks of code.
A Header routine to enter ISR. It must be:
1) STMFD sp!,{r5,lr} The workspace r5 plus the current return address lr_irq
is pushed into the system stack.
2) MRS r5,spsr
Save the spsr into r5
3) STMFD sp!,{r5}
Save r5
4) MSR cpsr_c,#0x1F
Reenable IRQ, go into system mode
5) STMFD sp!,{lr}
Save lr_sys for the system mode
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